1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a bump for an electrical connection in a semiconductor device package and a method of manufacturing the same.
2. Description of the Related Art
Various techniques for packaging integrated circuit (IC) chips or semiconductor device chips integrated with ICs have been suggested in the semiconductor manufacturing arts. The increase of the integration density in semiconductor devices has led to the popularity of bump pad technology, particularly having a small pitch. Minimized and/or portable electronic appliances employing semiconductor device packages impose strict restrictions on the height of the resulting IC packages.
As the height, or bonding surface area, of a bump is decreased to conform with such height restrictions, device reliability is degraded. Also, when etching an Under Bump Metal (UBM) mounted as a lower layer of the bump after forming the bump, an undesirable under cut may occur. Such an under cut of the UBM is regarded as lowering the bonding force of the bump and degrading electrical reliability of the bump.
FIG. 1 is a sectional view illustrating a bump structure of a conventional semiconductor device.
Referring to FIG. 1, the conventional bump structure is formed by carrying out a semiconductor device manufacturing process on a wafer or a semiconductor substrate 10, and then performing a bump manufacturing process. A bump pad 20 disposed on the semiconductor substrate 10 is composed of a metal such as AI, which is electrically connected to an interconnect of the semiconductor device during an interconnecting process of the semiconductor device.
A passivation layer 30 partially exposing a surface of the bump pad 20 is formed, and a UBM 40 electrically connected to the bump pad 20 exposed by the passivation layer 30 is formed. The passivation layer 30 may be composed of polyimide. Thereafter, a resist pattern (not shown) exposing the UBM 40 on the bump pad 20 is introduced, and a bump 50 is formed on the UBM 40 exposed by the resist pattern using electroplating, etc. Then, the resist pattern is removed, and a portion of the UBM 40 exposed by the bump 50 is selectively removed, thereby completing the bump structure.
At this time, the selective removal of the exposed UBM 40 is performed using isotropic etching such as wet etching. When performing the wet etching, an undercut 60 is liable to occur in the UBM 40. The under cut 60 decreases a bonding area between the bump 50 and an underlying layer, thereby degrading the reliability of the bump 50. The decreased bonding force of the bump 50 causes a significant problem if a smaller bump size or bump pad pitch is required.
Currently, as the electronic appliances employing the semiconductor device packages are further reduced in size, especially for portable use, the package needs to be produced with a smaller height. However, if the height of the bump 50, for example the height of the FIG. 1 bump structure, is reduced, the reliability to the bump is likely to become degraded. Therefore, in order to embody a stable electrical connection in the reduced-height package, the bump 50 is required to have a diameter or a thickness greater than a prescribed level. Therefore, the restriction in the decrease of the bump thickness operates as a final factor that impedes further reduction of the package thickness.